1. Field of the Invention
Embodiments relate to an apparatus for and method of processing data, and more particularly, to an apparatus for and method of processing data, which may facilitate the design of software and hardware configured to set parameters and process signals and the arrangement of components in connection with a signal processing circuit configured to sequentially process input data signals.
2. Description of the Related Art
Parameters, such as filter coefficients and filter intensities, which are used to process signals, are given to a signal processing circuit configured to process various signals, such as an image signal indicating an image (a moving image or still image). That is, since the signal processing circuit processes signals in response to a given parameter, when the corresponding parameter is updated, the signal processing circuit may perform another processing operation in response to the updated parameter.
A technique of setting parameters used for processing digital signals using a register has been developed. An example of a technique of reading, by a direct memory access controller (DMAC), a parameter stored in a memory in response to an instruction of a central processing unit (CPU) and setting the parameter in the register is disclosed in Japanese Patent Laid-open Publication No. 2008-234065. Also, an example of a technique of reading, by a DMAC, a parameter stored in a memory by a processor and setting the parameter in a register is disclosed in Japanese Laid-open Publication No. 2009-123091.
FIG. 8 is a block diagram of a configuration of a conventional data processing apparatus 10. In the data processing apparatus 10, a CPU 12 may set (newly write/update) parameters of a register 14a configured to store a parameter corresponding to a data transmission circuit 16 configured to read a data signal from a bus 20 and registers 14b, 14c, and 14d configured to store parameters corresponding to respective signal processing circuits 18a, 18b, and 18c. That is, in the data processing apparatus 10, the CPU 12 may update the parameters stored in the registers 14b, 14c, and 14d so that the signal processing circuits 18a, 18b, and 18c can perform processing operations in response to the updated parameters.
In order that the CPU 12 may write parameters in the respective registers 14b, 14c, and 14d, software executed by the CPU 12 may need to comprehend addresses of the respective registers 14b, 14c, and 14d. Accordingly, as the number of the registers 14b, 14c, and 14d increases, a process of managing the addresses of the registers 14b, 14c, and 14d may become more complicated. This may increase a design burden of software or a circuit configured to drive the software. Also, when the number of signal processing circuits 18a, 18b, and 18c is increased or reduced or design of the signal processing circuits 18a, 18b, and 18c is varied in connection with the design of hardware, a decoding circuit of each of the registers 14b, 14c, and 14d should be reconfigured, thereby increasing a design burden of hardware.
According to a conventional implementation in the art (hereinafter, ″Conventional Implementation 1″) in which a DMAC reads a parameter stored in a memory and sets the parameter in a register based on an instruction of a CPU, the DMAC may set the parameter in the register in a single image processing module, which may correspond to one signal processing circuit shown in FIG. 8.
The Conventional Implementation 1 shown in FIG. 8 is not configured for a plurality of signal processing circuits that are configured to sequentially process data signals. Thus, when the Conventional Implementation 1 shown in FIG. 8 is applied to the plurality of signal processing circuits that are configured to sequentially process the data signals, the CPU gives instructions to the DMAC of each of the signal processing circuits. The Conventional Implementation 1 cannot solve the above-described problems of the conventional data processing apparatus 10.
Furthermore, according to another conventional implementation in the art (hereinafter, “Conventional Implementation 2”) in which a DMAC reads a parameter, previously stored by a processor in a memory, and sets the parameter in a register, a register controller, which is an external component of a group of image processing modules corresponding to each of the signal processing circuits of FIG. 8, may set the parameter with respect to the corresponding group of image processing modules. That is, since the configuration of a data processing apparatus using the Conventional Implementation 2 is not basically different from that of the conventional data processing apparatus of FIG. 8, the Conventional Implementation 2 may still bring about the above-described problems of the conventional data processing apparatus 10.